The present invention relates to semiconductor integrated circuits and, more particularly, to the fabrication of integrated circuits containing high aspect ratio trenches, especially for use in a memory cell.
A memory cell in an integrated circuit comprises a transistor with an associated capacitor. The capacitor consists of a pair of conductive layers separated by a dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor As the density of integrated circuits with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge it is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes more difficult.
With a limited fixed space or volume for the capacitor of a memory cell in a highly integrated memory cell, there are three techniques for increasing the amount of charge within a fixed space or area; namely, (1) decrease the thickness of the dielectric material, (2) change the dielectric material to one with a higher dielectric constant, and (3) increase the surface area of the space to be used for the capacitor. Only technique (3) is a viable solution because technique (1), reducing the thickness of the dielectric, increases leakage currents which may effect the memory retention performance of the capacitor and the reliability of the memory cell. Technique (2), changing the dielectric material to one with a higher dielectric constant, will only cause a slight improvement in charge storage because the dielectric constant of suitable alternative dielectric materials is only slightly higher than the dielectric constant of the material presently being used. Moreover, the substitution of alternative dielectric materials may be more complicated, more expensive and provide unknown fabrication problems. Accordingly, technique (3), increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored in a memory cell.
One known solution to increase the surface area of the capacitor is to form a trench capacitor. An increase in the depth of the trench increases the surface area of the capacitor. However, the depth of the trench is limited by present fabrication methods and tools. This problem is compounded by the forever increasing density of integrated circuits which further causes the width of the trench capacitor to be narrowed. To offset the loss of surface area by a reduction in the width, the depth of the trench must be further increased or etched to the point where it becomes aspect ratio dependent.
Aspect ratio dependent behavior of deep trench etching is due to two factors: (1) decrease in etch rate of the substrate, herein silicon, with depth due to reduced solid angle of neutral flux at the bottom of the trench; and (2) incomplete removal of a passivation film which builds up at the bottom of the trench and blocks further etching of the trench. This second factor is due to decreasing ion energy at high aspect ratios and is caused by inelastic scattering of ions from the walls of the trench being etched. An etch stop occurs when the passivation film blocks further etching of the substrate. At very high aspect ratios, factor (2) dominates the slowing the etch rate of the substrate and solutions to overcome factor (1) become ineffective and preclude achieving the desired high aspect ratio trench.
One prior art solution to aspect ratio dependent behavior problem of deep trench etching, as described in U.S. Pat. No. 6,127,278, is to use a sequential multi-step etch, using in the first etch step an etchant composition of HBr and O2, followed by a second etch step using as the etchant a composition of a fluorine-containing gas, HBr and O2. The first etch step allows the formation of a passivation film of the side walls and bottom of the trench being etched while the second etch step removes the passivation film from the side walls and the bottom of the trench during etching by the second etchant. However, the etchant gases of the first etch step does not include any fluorine containing gas which has the advantage of reducing erosion of the hard mask, such as silicon oxide, but the disadvantage of limiting the depth of the trench and the necessity of adding a fluorine containing gas during the second step.
With increasing density of integrated circuits, especially integrated memory circuits, it is critical to have a simple fabrication technique which is easily adaptable for manufacturing a high aspect ratio trench. Accordingly, it is an object of the present invention to design a process for fabricating a high aspect ratio trench in which the formation of a passivation film at the bottom of the trench being etched does not limit the depth of the trench and the throughput of the etching process is high due to its simplicity of the process. Further, it is object of the present invention to design a process for etching high aspect ratio trenches with reduced build-up of a passivation film in the bottom of the trench being etched and is easily removed.
To achieve these and other objects, a fabrication process of the present invention for forming a high aspect ratio deep trench (DT), such as a deep trench capacitor, comprises reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step, for at least one short period of time, of increasing the concentration of fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power to remove the passivation film in the bottom of the trench while essentially leaving the passivation film on the side walls of the trench. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner. Specifically, the fluorine rich etching plasma, for removing the passivation film at the bottom of the trench, is exposed to the passivation film for a time in the range of two (2) to twelve (12) seconds and at a reactor chamber pressure of less than 100 millitorr or between a range of about 1 to about 100 millitorr and a RF power of less than 500 W or between a range of about 200 to about 500 W.